Bucket bridge delay line with error compensation

ABSTRACT

A capacitive delay device comprising a sequence of capacitances, in which information is transferred by charge transfer. The device is provided with at least one auxiliary store which has been connected between a first and a second capacitance, whilst after a charge transfer between the capacitances a residual charge transfer takes place between the first capacitance and the auxiliary store, after which the charge stored in the auxiliary store and in the second capacitance is transferred to a capacitance succeeding the second capacitance.

United States Patent 1 Sangster 1 .Eime 5,1973

[54] BUCKET BRIDGE DELAY LINE WITH ERROR COMPENSATION [75] Inventor: Frederik Leonard Johan Sangster,

Emmasingel, Eindhoven, Netherlands [73] Assignee: U.S. Philips Corporation, New

York, N.Y.

[22] Filed: Mar. 13, 1972 [21] Appl. No.: 234,365

Related U.S. Application Data [63] Continuation of Ser. No. 88,672, Nov. 12, 1970,

abandoned.

[30] Foreign Application Priority Data Sept. 25, 1970 Netherlands ..7014137 [52] U.S. Cl ..307/293, 307/221 D, 307/246, 307/251, 307/304 [51] Int. Cl. ..I-I03k 17/26 [58] Field of Search .l307/221 R, 221 C,

[56] References Cited UNITED STATES PATENTS 3,252,009 5/1966 Weimer ..307/22l C 3,474,260 10/1969 Frohbach ..307/221 R 3,546,490 12/1970 Sangster ..307/246 X Primary ExaminerStanley D. Miller, Jr. Attorney-Frank R. Trifari [57] ABSTRACT A capacitive delay device comprising a sequence of capacitances, in which information is transferred by charge transfer. The device is provided with at least one auxiliary store which has been connected between a first and a second capacitance, whilst after a charge transfer between the capacitances a residual charge transfer takes place between the first capacitance and the auxiliary store, after which the charge stored in the auxiliary store and in the second capacitance is transferred to a capacitance succeeding the second capacitance.

4 Claims, 4 Drawing Figures Pmmw SHEET 1 OF 3 IN VENTOR. FREDE RI K L-J- SANG STER BY 2 6. .M A NT BUCKET BRIDGE DELAY LINE WITII ERROR COMPENSATION This is a continuation of application Ser. No. 88,672, filed Nov. 12, 1970, now abandoned.

The invention relates to a device for delaying a train of signal samples of an electrical signal. The device comprises a sequence of stages which each include a first and a second capacitance interconnected by means of the main current path of at least one transistor. The second capacitance of each stage forms the first capacitance of the succeeding stage, while input electrode circuit of the transistor includes the first capacitance and its output electrode circuit includes the second capacitance. A switching voltage source is arranged to be connected between the control electrode of the transistor and that terminal of the first capacitance which is not connected to the input electrode of the transistor. In a known arrangement of this kind, as is described in Netherlands Patent Application No. 6,805,705, corresponding to US. application, Ser. No. 817,690, filed Apr. 21, 1969, the transistor is a field effect transistor. The field effect transistors are interconnected in groups so as to form junction points to which switching signals are applied which are ascendingly shifted in phase in the order of the numbers of the junction points.

Applicant recognizes the problem that when a large number of stages are used satisfactory operation is interfered with by the fact that in each stage of the arrangement a slight degradation of sudden voltage changes occurs. This means that when the input voltage abruptly changes from volts to V volts, the output sig nal at the output of the arrangement changes from 0 volts to (V 8) volts, where 6 is the error voltage. If subsequently the input signal remains at the value of V volts, the output signal will also assume this value. The said effect deleteriously affects the frequency characteristic of the device.

It is an object of the present invention to provide a solution of the said problem and a device according to the invention is characterized in that in at least several stages the first capacitance is also connected through an auxiliary store to the second capacitance of a succeeding stage, the said auxiliary store being controlled so that a charge transfer between the first capacitance and the auxiliary store takes place only after a charge transfer has taken place between the first and second capacitances, the charges stored in the auxiliary store and in the second capacitance being then transferred to the second capacitance of the succeeding stage.

The invention is based on the recognition that the said signal degradation is due to the fact that the threshold voltage of a transistor depends on the transferred signal value A V. When a comparatively small number of stages is used this effect will not be troublesome, but when a large number of stages, for example several hundreds of stages, are used it will be highly troublesome. The effect will be particularly strong when the transistors used are field effect transistors. This is due to the fact that electrostatic reaction takes place from the drain electrode by way of the substrate on the channel between the source electrode and the drain electrode of the field effect transistor used, and that on the other hand, the length of the channel slightly depends on the voltage at the drain electrode. In field effect transistors having a high-resistivity substrate the electrostatic reaction is the dominant factor,

whereas in field effect transistors having a lowresistivity substrate the second effect is dominant.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 shows the known arrangement,

FIG. 2 shows the voltage wave forms at different points in the known arrangement,

FIG. 3 shows an embodiment of an arrangement according to the invention, and

FIG. 4 shows the voltage wave forms at various points in the arrangement of FIG. 3.

In the known delay device shown in FIG. 1, the main current paths of the field effect transistors T T T are connected in series. A capacitor C has been connected between the drain and the gate of the transistor T A capacitor C1 has been connected between the drain and the gate of the transistor T,. A capacitor C, has been connected between the drain and the gate of the transistor T The gate of the transistor T has been connected to an output S of a switching voltage source S The gates of the transistors T and T have been connected to an output S of the switching voltage source S A diode D has one terminal connected to the drain of the transistor T, and the other terminal connected to the output S of the switching voltage source S The source of the transistor T has been connected to a point of constant potential through the series combination of a resistor R an input votage source V, and a direct-voltage source E The operation of the known arrangement will be described with reference to FIG. 2. FIGS. 2a and 2b show the voltage waveforms at the outputs S and S respectively. These voltages are symmetrical squarewave voltages having a maximum of 0 volts and a minimum of E volts. During the time in which the voltage at the point S is negative with respect to ground, i.e. during time intervals r r 1' and 1 in FIG. 2C, information about the value of the input signal V, is transferred to the capacitor C During the time interval 1' the input signal Vi is small, whereas during the time interval 1 and the following time intervals the input signal V, is large. During the time interval 1 there will flow through the transistor T a current of about V,/R amperes, where V, is the value of the input signal during the time interval 7 under consideration and R is the resistance of the resistor of FIG. 1. The said current will cause the voltage at the drain of said transistor T to increase by an amount Av see FIG. 2d. During the time interval 7 the capacitor C is discharged through the transistor T until the voltage across this capacitor has become equal to (EV volts, where' V is the threshold voltage of the transistor T the value of this threshold voltage being determined by the signal value AV During the time interval 7., charge is again supplied to the capacitor C through the transistor T so that the voltage at the drain of the transistor T will rise by an amount Av see FIG. 2d. During the time interval 1' the capacitor C is discharged through the transistor T until the voltage across this capacitor has become equal to (E-V' volts, where V',,, is that theshold voltage of the transistor T, which is associated with the signal value AV It has been found that the threshold voltage V,, associated with the signal value AV: exceeds the threshold voltage V associated with the signal value AV by an amount of 8 volts. This means that the voltage drop across the capacitor C which occurs during the time interval 1-,, will be equal to (AV 6) volts instead of to AV volts. At the instant at which the time interval 1-,, begins the voltage at the drain of the transistor T will be equal to 2EV,,) 6 volts, see FIG. 2d. At the end of the said time interval, the voltage at the drain of the transistor T will be equal to {-(ZE V,,) 6 AV volts. Consequently,

the voltage drop across the capacitor C will be equal to AV volts during this time interval.

During the time interval 1 the capacitor C, is charged throught the transistor T, until the voltage across this capacitor has risen by an amount of AV, volts, see FIG. 2e. During the time interval 1-,, the capacitor C, is discharged through the transisitor T until the voltage across this capacitor has become equal to (E--V,,) volts, where V is the threshold voltage of the transistor T associated with the signal value AV,. During the time interval 7 the capacitor C, is charged through the transistor T,. The voltage rise across the capacitor C, will be equal to the voltage drop across the capacitor C during the time interval under consideration. Consequently, the said voltage rise will be equal to (AV, 6) volts. During the time interval 1-,, the capacitor C, is discharged through the transistor T until the votage across this capacitor has become equal to (EV" volts, where V",, is the threshold voltage of the transistor T associated with the signal value (AV, 6). Since 8 is much smaller than AV we have to a good approximation V, V,,. This means that the voltage drop across the capacitor C, during the time interval 1 will be equal to (AV 2 8) volts instead of to AV, volts, as it should have been. A simple calculation shows that the voltage drop across the capacitor C of the capacitive store of FIG. 1, which voltage drop corresponds to the voltage drop (AV 8) volts across the capacitor C during the time interval 7 will be equal to (AV, n. 8) volts, where n is the number of the capacitor C,,. However, this will hold only if n. 6 is small compared with AV,. If n. 6 becomes comparable to AV i.e. if n is large, the corresponding voltage drop will be equal to (1- 8)" volts. However, if it. 6 becomes comparable to the signal value AV second-order and third-order effects also will occur. This means that in contradistinction to the example discussed with reference to FIGS. 2d and 2e in which one signal value only was not correct (see the interval 1,, of FIG. 2d and the interval 1,, in FIG. 2e) at least two successive signal values will not be correct, as is shown diagrammatically in FIG. 2f. In this Figure the signal values during the intervals 1', and 1-, are not correct. During the time interval 1-,, the signal value is equal to (AV, 5 volts, and during the time interval 1-, the signal value is equal to (AV -6 volts. Not before the interval r,,, will the signal value be correct and equal to AV volts.

FIG. 3 shows a delay device according to the invention. The main current paths of transistors T,,, T,, T T T, have been connected in series. The source of the transistor T has been connected to a point of constant potential through the series combination of a resistor R and a signal voltage source V,. Storage ca pacitor C C,, C C and C,, have been included between the drain and gate electrodes of the transistors T,,, T,, T T and T, respectively. The gates of the transistors T and T, have been connected to a signal out put 2 of a signal voltage source S,,, and the gates of the transistors T,, T, and T, have been connected to an output 1 of the switching voltage source S,,. A diode D has been connected between the drain of the transistor T,, and the output 2 of the switching voltage source S,,. The capacitor C has also been connected, through an auxiliary store I, to an additional source of the transistor T The capacitor C, has also been connected, through an auxiliary stor II, to an additional source of the transistor T and the capacitor C, has also been connected, through an auxiliary store III, to an additional source of the transistor T,,. The auxiliary stores each include a field effect transistor between the gate and drain of which a capacitor has been included. The gates of transistors T and T of the store stages I and III respectively have been connected to the output 3 of the switching voltage source S,,, and the gate of a transistor T of the store stage II has been connected to the output 4 of the switching voltage source S,,. The operation of circuit arrangement shown in FIG. 3 will be described with reference to FIG. 4.

It is assumed that during the time intervals preceeding the time interval t, the input signal V,- has an amplitude of 0 volts. This means that during these time intervals the transistor T was non-conductive, and no charge flowed into the capacitor C Hence, during the time intervals t, and t the voltage across the capacitor C will be equal to -(E V volts, where V, is the threshold voltage of the transistor T,, see FIG. 4e. During the time intervals t and t, the voltage at the gate of the transistor T is equal to E volts, see FIG. 4b. It is further assumed that during the time intervals t and t, the input signal has a positive amplitude differing from 0. During the said intervals the transistor T will be conductive. At the end of the interval t, the voltage across the capacitor C 0 will have increased by an amount of AV volts, see FIG. 4e. During the time intervals t and t, the voltage at the gate of transistor T, is equal to E volts, see FIG. 4a, and the voltage at the gate of the transistor T is equal to 0 volts. During the said time intervals the transistor T, is conductive and the transistor T is non-conductive. During the time interval t the capacitor T is discharged until the voltage at a point 5 of the circuit arrangement has become equal to (E-'V,, 5) volts, see FIG. 4e, where V 6) is the threshold voltage of the transistor T, associated with the sudden signal change A V. A voltage V at a point 7 of the circuit arrangement will have increased by an amount (AV 8) volts during the time interval under consideration, see FIG. 4g. During the time interval t the transistor T,, will be conductive. During this time interval the charge 8 .0 remaining in the capacitor C,, during the time interval t is transferred substantially entirely to the capacitor C,,

through the transistor T,,. As a result, a voltage V, at a point 6 of the circuit arrangement will rise by an amount of 8/h volts. Owing to this rise the threshold voltage of the transistor T,, will slightly increase, so that the final voltage across the capacitor C will be equal to (IV, +d/h 6) volts, where dis 8/V Thus, the provision of the auxiliary store I connected between the capacitor C and the capacitor C ensures that the error which occurs in the reference voltage across the capacitor C has been reduced by a factor d/h. For simplicity the error d/h 8 will be neglected. During the time interval t charge is transferred from the capacitor C, to the capacitor C Simultaneously charge is transferred from the capacitor C,, to the capacitor C A charge of C. (A V 2 8) coulombs will flow from the capacitor C, to the capacitor C A charge of 8.C coulombs will flow from the capacitor C to the capacitor C As a result, the voltage across the capacitor C will rise by an amount of (A V 8) volts, see FIG. 4h. The voltage across the capacitor C will drop until it has become equal to (EV 8) volts. Hence, the error in the reference level across the capaitor C will be equal to 8 volts. During the time interval t charge is transferred from the capacitor C 1 to the capacitor C The voltage across the latter capacitor will rise by an amount of d/h volts. During the time interval t charge will be transferred between the capacitors C and C and between the capacitors C and C The voltage across the capacitor C will drop until it has become equal to (E V 6) volts, see FIG. 4h. Thus, in this case also the error in the reference level will be equal to 8 volts. If the said error of d/h. 8 volts in the reference voltage across the capacitor C is not neglected, a simple calculation shows that the error in the reference voltage across the capacitor C, will be equal to 8(1n d/h) volts, where n is the number of the capacitor under consideration. With, for example, d l/300 h 1/10 and n 100 the error in the reference voltage will be 1 percent and hence will be negligible. With d 1/300 and n 100, in the arrangement shown in FIG. 1 the error in the reference value will be 30 percent, which is unacceptably large.

In the embodiment shown in FIG. 3, in each storage stage the source of the transistor has been directly connected to the first capacitor. Alternatively, however, the source may be connected to the first capacitor through the main current path of a second field effect transistor. Further the source of the transistor of each of the auxiliary storage stages I, II and III may also be connected to the pertinent capacitor through the main current path of a field effect transistor. This ensures that the error in the reference voltage will be further reduced.

It will be appreciated that the invention is not restricted to the examples described and that to a person skilled in the art many modifications will be possible without departing from thescope of the invention. For example, both bipolar and field effect transistors may be used. Also, field effect transistors both of the enhancement type and of the depletion type may be used. Further, a substrate of low resistivity, for example 1 ohm, may be used and the channel length of the field effect transistors may be large, with a consequent additional reduction of the reaction. Moreover, the device described with reference to FIG. 3 may advantageously be used to realize a filter for electrical signals. In addition, the usual input and output circuits may be used in conjuction with the device described. Furthermore, at least two of the said devices may be connected in parallel so as to have common inputs and/or outputs.

What is claimed is:

1. A circuit comprising a plurality of serially coupled stages, each of said stages comprising a transistor having a main current path between at least first input and second output conduction electrodes, and one control electrode for controlling the conduction therein, each of said second conduction electrodes being coupled to the first conduction electrode of the transistor of the succeeding stage, a capacitive means having a first end coupled to said second conduction electrode and a second end, means for transferring charge from one of said capacitors to the succeeding stage capacitor comprising means for applying switching pulses to said second end of said capacitor and to said control electrode, thereby rendering said conduction path conductive, each of said stages except the first stages of said plurality of serially coupled stages further comprising auxiliary store means coupled to said first conduction electrode and to an input electrode said succeeding stage for storing charge from said capacitor after said transfer and for transferring said stored charge to the succeeding stage capacitor; whereby errors occurring during said first recited charge transfer are reduced.

2. A circuit as claimed in claim 1 wherein each of said transistors comprises second input conduction electrode, each of said auxiliary storing means being coupled to said succeeding stage second input electrode.

3. A device as claimed in claim 1, wherein the auxiliary store means comprises an auxiliary transistor having a main conduction path having first and second conduction terminals and a control input terminal wherein the current in the main conduction path is a function of voltage between said first conduction terminal of the main conduction path and the control input terminal, and a capacitor connected between the control input terminal and said second conduction terminal of the main conduction path, wherein the capacitance of the capacitor in the auxiliary store is smaller than the capacitance in the delaying stages.

4. A circuit as claimed in claim I wherein said applying means applies switching pulses of opposite polarity to adjacent stages. 

1. A circuit comprising a plurality of serially coupled stages, each of said stages comprising a transistor having a main current path between at least first input and second output conduction electrodes, and one control electrode for controlling the conduction therein, each of said second conduction electrodes being coupled to the first conduction electrode of the transistor of the succeeding stage, a capacitive means having a first end coupled to said second conduction electrode and a second end, means for transferring charge from one of said capacitors to the succeeding stage capacitor comprising means for applying switching pulses to said second end of said capacitor and to said control electrode, thereby rendering said conduction path conductive, each of said stages except the first stages of said plurality of serially coupled stages further comprising auxiliary store means coupled to said first conduction electrode and to an input electrode said succeeding stage for storing charge from said capacitor after said transfer and for transferring said stored charge to the succeeding stage capacitor; whereby errors occurring during said first recited charge transfer are reduced.
 2. A circuit as claimed in claim 1 wherein each of said transistors comprises second input conduction electrode, each of said auxiliary storing means being coupled to said succeeding stage second input electrode.
 3. A device as claimed in claim 1, wherein the auxiliary store means comprises an auxiliary transistor having a main conduction path having first and second conduction terminals and a control input terminal wherein the current in the main conduction path is a function of voltage between said first conduction terminal of the main conduction path and the control input terminal, and a capacitor connected between the control input terminal and said second conduction terminal of the main conduction path, wherein the capacitance of the capacitor in the auxiliary store is smaller than the capacitance in the delaying stages.
 4. A circuit as claimed in claim 1 wherein said applying means applies switching pulses of opposite polarity to adjacent stages. 